`timescale 1ns / 1ps


module top();


reg clk_1GH = 1'b0;
reg clk_en = 1'b0;

wire clk_1GH_w = clk_1GH;
wire clk_en_w = clk_en;

wire DCLK0;
wire FCLK, DCLK;

wire L_P, L_N;

AD_CLK u_ad_clk(
    .clk_1GH(clk_1GH_w),
    .clk_en(clk_en_w),
    .FCLK(FCLK),
    .DCLK(DCLK),
    .DCLK0(DCLK0),
    .L_P(L_P),
    .L_N(L_N)
);


initial begin
	$dumpfile("wave.vcd");
	$dumpvars(0,top);
end

initial begin
    forever #1 clk_1GH = ~clk_1GH;
end

initial begin
    #100     clk_en = 1'b0;
    #100    clk_en = 1'b1;
    #1000   clk_en = 1'b0;
	$finish;
end


endmodule
